In high speed circuits, complementary clocking signals are often used to improve the performance of clocked elements (i.e. flip-flops, latches, etc.). Prior approaches to generating complementary clocks used two dividers with the output of the first being inverted and fed into the input of the second. This approach is performance limited by the fact that sufficient setup time is required into the second stage divider before another clock pulse can be received.
At very high speeds, clock skew between complementary clock signals becomes a significant performance issue in clocked elements.
It is an object of the present invention to provide a means for generating high speed complementary clock signals from a single clock input.
It is another object of the present invention to provide a circuit that uses dynamic clocked elements.
It is yet another object of the present invention to provide a clock recovery circuit that eliminates an inverted feedback path.